1. Field of Invention
The present invention relates in general to mixed digital-analog circuits and in particular to digital to differential converters and digital to analog converters using the same.
2. Background of Invention
Mixed signal circuit designs, generally integrating both analog and digital circuit blocks on the same integrated circuit chip, have proliferated over the last decade. A significant number of these designs, such as digital to analog converters (DACs), require the conversion of single-ended digital data into differential analog signals. Often these differential analog signals must be generated in the presence of an arbitrary capacitive load and variations in supply voltage, temperature, and process corner. Circuit operation under these conditions typically leads to distortion, spiking, and gain error in the resulting voltage or current output signals.
In the case of a typical high-speed current steering DAC, an analog output is generated by summing binary weighted currents switched by transistors controlled by the incoming digital codewords. As the slew rate of the logic signals increases as digital technology advances, the speed and accuracy of the switching transistors becomes more critical if distortion in the output signal is to be minimized. One way of addressing the problem of distortion is to generate differential analog signals from the single-ended digital data and then use the differential signals to drive a differential transistor pair (diffpair) in a relatively distortion-less manner. The diffpair circuits in turn are the basic building blocks of a current steering DAC, which switch the weighted currents.
Various techniques have therefore been developed for converting high-speed, single-ended logic levels to accurate, low distortion, differential analog signals. These techniques ensure that the output signals precisely track the input signal duty cycle and have substantially equal output rising and falling slew rates for the output signals. The existing techniques are still subject to significant output distortion, especially in high-speed circuits and/or in the presence of increased capacitive loads. In sum, new circuits and methods are required for converting digital logic levels into differential analog levels with minimal distortion. These new circuits and methods should be particularly useful in low-distortion digital to analog converters, although not necessarily limited thereto.
The principles of the present invention are embodied in digital to differential analog converter cells and multiple-bit digital to analog converters using the same. According to one particular embodiment, converter circuitry is disclosed for converting digital data into differential analog signals. The converter circuitry includes a temperature and process independent bias voltage generator for generating a bias voltage and a digital to differential converter for converting a digital word into differential voltages. The digital to differential converter includes first switching circuitry controlled by the digital word for selectively coupling a first output node to the bias voltage and a second output node to a supply voltage. Second switching circuitry controlled by a complement of the digital word selectively couples the first output node to the supply voltage and the second output node to the bias voltage. The first and second pairs of switches substantially simultaneously conduct at a differential crossover voltage at the first and second output nodes.
Application of the present inventive principles realize substantial advantages over the prior art. The digital to differential analog converter output switches provides the averaging effect that results in minimal distortion in the analog output signal. Furthermore, bias voltage and current circuitry that is temperature, process, and supply independent ensures that the gain variation of the current steering differential pair DAC cell is minimal. Also, the disclosed circuits are scalable such that varying loads, such as weighted current steering cells, are supported by a direct scaling of transistor sizes.